2011年8月15日月曜日

Cortex-M0 NUC120-SDKボード味見(3)

HOS-V4a-20110405のつづき
NUC120-SDK でADC0, ADC1を使用してみる。
ADCを周期的に起動するには
1)周期タスク
2)通常タスクでdly_tsk(wait)
3)通常タスクでタイマー割り込みでADC起動
などの方法があるが
今回はTMR0周期割り込みでADC起動、ADC終了割り込みでAdc_Task()起床とした。
ADC1 はフォトリフレクタ接続で PB12で赤外LEDを点灯制御しています。
http://akizukidenshi.com/catalog/g/gI-00276/

---------
sample/arm/nuc120/adc.c
/**
* Sample program for Hyper Operating System V4 Advance
*
* @file sample.c
* @brief %jp{サンプルプログラム}%en{Sample program}
*
* Copyright (C) 1998-2011 by Project HOS
* http://sourceforge.jp/projects/hos/
*/

#include <stdlib.h>
#include <string.h>
#include "kernel.h"
#include "kernel_id.h"
#include "uart.h"
#include "nuc120_reg.h"

extern volatile long OSTick;

/* サンプルタスク dly_tsk() */
void Led_PC2(VP_INT exinf)
{
for(;;){
*REG_GPIOC_DOUT ^= 0x04;/* PC2 */
dly_tsk(500);
}
}

/* 周期タスク */
void Led_PC3(VP_INT exinf)
{
*REG_GPIOC_DOUT ^= 0x08;/* PC3 */
}


/** %jp{サンプルタスク} */
void Adc_Task(VP_INT exinf)
{
int value;
/* ADC */
*REG_GPA_MFP |= 3;/* ADC0,ADC1 */
/* reset ADC */
*REG_SYS_IPRSTC2 |= (1<<28);/* ADC_RST */
*REG_SYS_IPRSTC2 &= ~(1<<28);

/* ADC clock source */
*REG_CLKSEL1 &= ~(3<<2);

/* Set ADC divisor */
*REG_CLKDIV &= (255<<16);
*REG_CLKDIV |= (11<<16);
/* ADC engine clock enable */
*REG_APBCLK |= (1 << 28); /* ADC CLK Enable */

/* ADC enable */
*REG_ADC_ADCR &= ~(1<<10);
*REG_ADC_ADCR &=~(3<<2);
*REG_ADC_ADCR |= 3;/* ADIE+ADEN */
*REG_ADC_ADCHER = 2;/* ADC1 */

ena_int(29);

/* TMR0 */
*REG_CLKSEL1 &= ~(7<<8); /* use ExClk:12MHz */
*REG_APBCLK |= (1 << 2); /* TMR0 CLK Enable */

*REG_TMR_TCMPR0 = 1000000/100;/* 100Hz */
*REG_TMR_TDR0 = 0x00;

*REG_TMR_TCSR0=0x00;
*REG_TMR_TCSR0 =(1<<27) | (1<<16) | (11); /* MODE=01 TDR_EN=1 Prescale=12 */
*REG_TMR_TCSR0 |= (1<<30);/* CEN */
*REG_TMR_TCSR0 |= (1<<29);/* IE */

ena_int(8);

for(;;)
{
*REG_GPIOB_DOUT &= ~(1<<12);/* PB12 LED on */

slp_tsk();

*REG_GPIOB_DOUT |= (1<<12);/* PB12 LED off */

if (*REG_ADC_ADSR & (1<<9)) { /* VALID */
value = *REG_ADC_ADDR1 & 0xffff;
/** %jp{状態表示} */
if(value>10){
wai_sem(SEMID_UART);
/* %jp{文字列生成} */
printk("%d %d\n",OSTick,value);

sig_sem(SEMID_UART);
}
}
}
}


void ADC_Isr(VP_INT exinf)
{
*REG_ADC_ADSR |= 7;/* Clear Flags CMP/ADF */
/* slp_tsk() 起床 */
iwup_tsk(TSKID_ADC);
}


void TMR0_Isr(VP_INT exinf)
{
/* ADC 起動 */
*REG_ADC_ADSR |= 7;/* Clear Flags CMP/ADF */
*REG_ADC_ADCR |= (1<<11);/* ADST */

*REG_TMR_TISR0 = 0x01; /* clear TIF */
}

/* end of file */

sample/arm/nuc120/system.cfg

/**
* Sample program for Hyper Operating System V4 Advance
*
* @file system.cfg
* @brief %jp{サンプルのコンフィギュレーション}
*
* Copyright (C) 1998-2006 by Project HOS
* http://sourceforge.jp/projects/hos/
*/


/* %jp{カーネル独自の設定}%en{kernel} */
KERNEL_HEP_MEM(256, NULL);
KERNEL_SYS_STK(256, NULL);
KERNEL_INT_STK(512, NULL);
KERNEL_RSV_TSKID(0);
KERNEL_RSV_SEMID(0);
KERNEL_RSV_FLGID(0);
KERNEL_RSV_DTQID(0);
KERNEL_RSV_MBXID(0);
KERNEL_RSV_MPFID(0);
KERNEL_RSV_MTXID(0);
KERNEL_RSV_CYCID(0);


/* %jp{OSタイマの設定}%en{OS timer} */
INCLUDE("\"ostimer.h\"");
ATT_INI({TA_HLNG, 0, OsTimer_Initialize});
DEF_INH(15, {TA_HLNG, OsTimer_Isr}); /* 15:SysTick */

ATT_INI({TA_HLNG, 0, UART0_Initialize});
DEF_INH(28, {TA_HLNG, UART0_Isr}); /* 28:UART0 */

DEF_INH(24, {TA_HLNG, TMR0_Isr}); /* 24:TMR0 */
DEF_INH(45, {TA_HLNG, ADC_Isr}); /* 45:ADC */

/* %jp{サンプル}%en{Sample program} */
INCLUDE("\"sample.h\"");
ATT_INI({TA_HLNG, 0, Sample_Initialize});
CRE_TSK(TSKID_SAMPLE1, {TA_HLNG | TA_ACT, 1, Sample_Task, 2, 512, NULL});
CRE_TSK(TSKID_SAMPLE2, {TA_HLNG | TA_ACT, 2, Sample_Task, 2, 512, NULL});
CRE_TSK(TSKID_SAMPLE3, {TA_HLNG | TA_ACT, 3, Sample_Task, 2, 512, NULL});
CRE_TSK(TSKID_SAMPLE4, {TA_HLNG | TA_ACT, 4, Sample_Task, 2, 512, NULL});
CRE_TSK(TSKID_SAMPLE5, {TA_HLNG | TA_ACT, 5, Sample_Task, 2, 512, NULL});
CRE_TSK(TSKID_ADC, {TA_HLNG | TA_ACT, 5, Adc_Task, 3, 512, NULL});
CRE_TSK(TSKID_LED, {TA_HLNG | TA_ACT, 0, Led_PC2, 7, 512, NULL});
CRE_CYC(CYCID_LED, {TA_HLNG , 0, Led_PC3, 250, 0});
CRE_SEM(1, {TA_TFIFO, 1, 1});
CRE_SEM(2, {TA_TFIFO, 1, 1});
CRE_SEM(3, {TA_TFIFO, 1, 1});
CRE_SEM(4, {TA_TFIFO, 1, 1});
CRE_SEM(5, {TA_TFIFO, 1, 1});
CRE_SEM(SEMID_RAND, {TA_TFIFO, 1, 1});
CRE_SEM(SEMID_UART, {TA_TFIFO, 1, 1});
CRE_FLG(FLGID_UART, {TA_TFIFO | TA_WSGL, 0});


/* end of file */

sample/arm/nuc120/nuc120_reg.h
#ifndef _NUC120_DEF_
#define _NUC120_DEF_

#define CLK_BA (0x50000200) /* System Clock Control Register */
#define REG_PWRCON ((volatile UW *)(CLK_BA+0x00)) /* PWRCON Register */
#define REG_AHBCLK ((volatile UW *)(CLK_BA+0x04)) /* AHBCLK Register */
#define REG_APBCLK ((volatile UW *)(CLK_BA+0x08)) /* APBCLK Register */
#define REG_CLKSEL0 ((volatile UW *)(CLK_BA+0x10)) /* CLKSEL0 Register */
#define REG_CLKSEL1 ((volatile UW *)(CLK_BA+0x14)) /* CLKSEL1 Register */
#define REG_CLKDIV ((volatile UW *)(CLK_BA+0x18)) /* CLKDIV Register */
#define REG_CLKSEL2 ((volatile UW *)(CLK_BA+0x1c)) /* CLKSEL2 Register */
#define REG_PLLCON ((volatile UW *)(CLK_BA+0x20)) /* PLLCON Register */

#define GCR_BA (0x50000000) /* System Manager Control Register */
#define REG_SYS_RSTSRC ((volatile UW *)(GCR_BA+0x004)) /* GPIO Register */
#define REG_SYS_IPRSTC1 ((volatile UW *)(GCR_BA+0x008)) /* GPIO Register */
#define REG_SYS_IPRSTC2 ((volatile UW *)(GCR_BA+0x00c)) /* GPIO Register */
#define REG_GPA_MFP ((volatile UW *)(GCR_BA+0x030)) /* GPIO Register */
#define REG_GPB_MFP ((volatile UW *)(GCR_BA+0x034)) /* GPIO Register */
#define REG_GPC_MFP ((volatile UW *)(GCR_BA+0x038)) /* GPIO Register */
#define REG_GPD_MFP ((volatile UW *)(GCR_BA+0x03c)) /* GPIO Register */
#define REG_GPE_MFP ((volatile UW *)(GCR_BA+0x040)) /* GPIO Register */

#define REG_WRPROT ((volatile UW *)(GCR_BA+0x100)) /* REGWRPROT Register */

#define GP_BA (0x50004000) /* System Manager Control Register */
#define REG_GPIOA_PMD ((volatile UW *)(GP_BA+0x000)) /* GPIOB Register */
#define REG_GPIOA_DOUT ((volatile UW *)(GP_BA+0x008)) /* GPIOB Register */
#define REG_GPIOB_PMD ((volatile UW *)(GP_BA+0x040)) /* GPIOB Register */
#define REG_GPIOB_DOUT ((volatile UW *)(GP_BA+0x048)) /* GPIOB Register */
#define REG_GPIOC_PMD ((volatile UW *)(GP_BA+0x080)) /* GPIOB Register */
#define REG_GPIOC_DOUT ((volatile UW *)(GP_BA+0x088)) /* GPIOB Register */

#define ADC_BA (0x400e0000) /* ADC Registers */
#define REG_ADC_ADDR0 ((volatile UW *)(ADC_BA+0x000)) /* ADC0 Register */
#define REG_ADC_ADDR1 ((volatile UW *)(ADC_BA+0x004)) /* ADC1 Register */
#define REG_ADC_ADDR2 ((volatile UW *)(ADC_BA+0x008)) /* ADC2 Register */
#define REG_ADC_ADDR3 ((volatile UW *)(ADC_BA+0x00c)) /* ADC3 Register */
#define REG_ADC_ADDR4 ((volatile UW *)(ADC_BA+0x010)) /* ADC4 Register */
#define REG_ADC_ADDR5 ((volatile UW *)(ADC_BA+0x014)) /* ADC5 Register */
#define REG_ADC_ADDR6 ((volatile UW *)(ADC_BA+0x018)) /* ADC6 Register */
#define REG_ADC_ADDR7 ((volatile UW *)(ADC_BA+0x01c)) /* ADC7 Register */
#define REG_ADC_ADCR ((volatile UW *)(ADC_BA+0x020)) /* ADCR Register */
#define REG_ADC_ADCHER ((volatile UW *)(ADC_BA+0x024)) /* ADCHER Register */
#define REG_ADC_ADSR ((volatile UW *)(ADC_BA+0x030)) /* ADSR Register */

#define TMR_BA01 (0x40010000) /* TMR01 */
#define REG_TMR_TCSR0 ((volatile UW *)(TMR_BA01+0x00)) /* UART Receiver Buffer Register */
#define REG_TMR_TCMPR0 ((volatile UW *)(TMR_BA01+0x04)) /* UART Transmitter Holding Register */
#define REG_TMR_TISR0 ((volatile UW *)(TMR_BA01+0x08)) /* UART Divisor Latch LSB and MSB Registers */
#define REG_TMR_TDR0 ((volatile UW *)(TMR_BA01+0x0c)) /* UART Divisor Latch LSB and MSB Registers */
#define REG_TMR_TCSR1 ((volatile UW *)(TMR_BA01+0x20)) /* UART Receiver Buffer Register */
#define REG_TMR_TCMPR1 ((volatile UW *)(TMR_BA01+0x24)) /* UART Transmitter Holding Register */
#define REG_TMR_TISR1 ((volatile UW *)(TMR_BA01+0x28)) /* UART Divisor Latch LSB and MSB Registers */
#define REG_TMR_TDR1 ((volatile UW *)(TMR_BA01+0x2c)) /* UART Divisor Latch LSB and MSB Registers */

#define UART0_BA (0x40050000) /* UART0 */
#define REG_U0RBR ((volatile UW *)(UART0_BA+0x00)) /* UART Receiver Buffer Register */
#define REG_U0THR ((volatile UW *)(UART0_BA+0x00)) /* UART Transmitter Holding Register */
#define REG_U0BAUD ((volatile UW *)(UART0_BA+0x24)) /* UART Divisor Latch LSB and MSB Registers */
#define REG_U0IER ((volatile UW *)(UART0_BA+0x04)) /* UART Interrupt Enable Register */
#define REG_U0ISR ((volatile UW *)(UART0_BA+0x1c)) /* UART Interrupt Identification Register */
#define REG_U0FCR ((volatile UW *)(UART0_BA+0x08)) /* UART FIFO Control Register */
#define REG_U0LCR ((volatile UW *)(UART0_BA+0x0c)) /* UART Line Control Register */
#define REG_U0MCR ((volatile UW *)(UART0_BA+0x10)) /* UART0 Modem Control Register */
#define REG_U0FSR ((volatile UW *)(UART0_BA+0x18)) /* UART FSR Register */
#define REG_U0ALTCON ((volatile UW *)(UART0_BA+0x2c)) /* UART */
#define REG_U0FUNSEL ((volatile UW *)(UART0_BA+0x30)) /* UART */

#endif
/* end of file */

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